1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection device. More particularly, the invention relates to an ESD protection device having a relatively lower trigger voltage and a relatively higher holding voltage.
2. Description of Related Art
The internal circuitry of contemporary semiconductor integrated circuits (ICs) is very sensitive to, and may be damaged by the application of elevated voltages or currents, such as those commonly induced by a discharge of static electricity (or an electro static discharge, “ESD”). When an elevated voltage or current induced by ESD reaches the material layers forming the internal circuitry of a semiconductor IC one or more insulating films may be destroyed or various conductive elements may be short-circuited by the voltage/current impulse. Such damage often destroys the semiconductor IC.
In order to prevent this phenomenon, most contemporary semiconductor ICs incorporate some form of ESD protection related to their Input/Output (I/O) circuitry. Generally speaking, ESD protection is designed to discharge the high voltages (and resulting currents) associated with ESD, thereby preventing the potentially damaging effects from reaching the internal circuitry of the semiconductor IC. A grounded gate NMOS (GGNMOS) or a semiconductor controlled rectifier (SCR) are common elements used to implement ESD protection.
Figure (FIG.) 1 is a schematic structural view a GGNMOS of the sort used in conventional ESD protection. Dual n+ regions 11 and 12 are formed in a p-type substrate 10 and separated across a gate electrode 14. A p+ region 13 is formed at a predetermined distance from n+ region 12 with an insulating region 15 interposed between n+ region 12 and p+ region 13. An I/O terminal (DQ) is connected to n+ region 11, with an n+ region 12, p+ region 13 and gate electrode 14 being connected to a first power voltage (e.g., ground voltage Vss in the illustrated example).
The operation of the GGNMOS shown in FIG. 1 will now be described.
When high voltage is applied to the I/O terminal DQ as the result of an ESD event, a breakdown occurs across the p-n junction between n+ region 11 and p-type substrate 10, such that current associated with the high voltage application flows through n+ region 11, p-type substrate 10 and p+ region 13. As a result, a forward bias is applied between p-type substrate 10 and n+ region 12, such that current flows from I/O terminal DQ to ground through n+ region 11, p-type substrate 10 and n+ region 12.
FIG. 2 is an equivalent circuit diagram for the GGNMOS shown in FIG. 1. Dual n+ regions 11 and 12 and gate electrode 14 form a drain, a source and a gate of an NMOS transistor N1, respectively. The n+ regions 11 and 12 and p-type substrate 10 form a collector, an emitter and a base of a junction transistor Q1, respectively. In FIG. 2, the element designated by “Rp” denotes an equivalent resistor associated with p-type substrate 10.
Operation of the equivalent circuit shown in FIG. 2 will now be described.
If more than a predetermined voltage (i.e., trigger voltage) at which breakdown occurs across the p-n junction between n+ region 11 and p-type substrate 10 is applied to the I/O terminal DQ, current flows through the collector and the base of the junction transistor Q1 and the resistor Rp. Due to this current, a base voltage for the junction transistor Q1 is raised to turn ON the junction transistor Q1, such that a large amount of current flows from the I/O terminal DQ to ground through the junction transistor Q1.
Consistent with the foregoing, in order to allow a larger amount of current to flow, the area occupied by the GGNMOS must be relatively large. However, implementing this relatively large GGNMOS is difficult given the contemporary drivers towards more dense element integration within semiconductor ICs. For this reason, the SCR has been proposed as a possible replacement for the GGNMOS in similar ESD protection circuits.
FIG. 3 is a schematic diagram of a SCR like those commonly used in conventional ESD protection. A n-well 21 is formed in a p-type substrate 20, and an n+ region 31 and a p+ region 32 are formed in n-well 21 spaced apart from each other. An n+ region 33 is formed to contact with both n-well 21 and p-type substrate 20 at a predetermined distance from p+ region 32. Separate insulating region 30 is interposed between n+ region 31 and p+ region 32 and between p+ region 32 and n+ region 33. An n+ region 34 is formed at a predetermined distance from n+ region 33, and a gate electrode 40 is formed on p-type substrate 20 between n+ region 33 and n+ region 34. A p+ region 35 is formed at a predetermined distance from n+ region 34, and insulating film 30 is interposed between n+ region 34 and p+ region 35. An I/O terminal DQ is connected to n+ region 31 and p+ region 32, and n+ region 34, p+ region 35 and gate electrode 40 are connected to ground voltage Vss.
The operation of the SCR shown in FIG. 3 will now be described.
If a high voltage associated with an ESD event is applied to the I/O terminal DQ, a breakdown occurs across the p-n junction between n-well 21 and p-type substrate 20, such that current flows through n+ region 31, n-well 21, p-type substrate 20 and p+ region 35. As a result, a forward bias is applied between p+ region 32 and n-well 21 by the current, such that the current flows through p+ region 32, n-well 21, and p-type substrate 20. Accordingly, a forward bias is applied between p-type substrate 20 and n+ region 34, such that current flows through n-well 21, p-type substrate 20 and n+ region 34.
FIG. 4 is a circuit diagram illustrating an equivalent circuit of the SCR shown in FIG. 3. Here, n-well 21, p-type substrate 20 and n+ region 34 form a collector, a base and an emitter of a junction transistor Q1, respectively. The p+ region 32, n-well 21 and p-type substrate 20 form a collector, a base and an emitter of a junction transistor Q2, respectively. The n+ region 33, gate electrode 40 and n+ region 34 form a drain, a gate and a source of an NMOS transistor N1, respectively. In FIG. 4, “Rn” denotes an equivalent resistor formed by n-well 21, and “Rp1” denotes an equivalent resistor formed by p-type substrate 20. The junction transistor Q1 is connected between the resistor Rn and ground voltage Vss, the junction transistor Q2 is connected between the I/O terminal DQ and the resistor Rp1, the base of the junction transistor Q1 is connected to the collector of the junction transistor Q2, the base of the junction transistor Q2 is connected to the collector of the junction transistor Q1, the NMOS transistor N1 is connected in parallel with the junction transistor Q1, and ground voltage Vss is applied to the gate of the NMOS transistor N1. The resistor Rn is connected to the I/O terminal DQ, and the resistor Rp1 is connected to ground voltage Vss.
FIG. 5 is a graph further illustrating the operation of the SCR shown in FIGS. 3 and 4. When a voltage applied to the I/O terminal DQ is less than a trigger voltage Vt, current is unlikely to flow since the SCR has a relatively high resistance value (graph section 1 of FIG. 5). If the applied voltage rises above the trigger voltage Vt due to an ESD event, a breakdown occurs in the p-n junction between n-well 21 and p-type substrate 20, such that current flows between nodes A and B (see, FIG. 4) and the voltage at the I/O terminal DQ abruptly decreased according to snapback phenomenon (graph section 2 of FIG. 5). When current flowing through the SCR increases above the holding current Ih, both junction transistors Q1 and Q2 are turned ON to discharge the relatively large current (graph section 3 of FIG. 5). Thus, the voltage apparent at the I/O terminal DQ of when both junction transistors Q1 and Q2 are turned ON is equal to the holding voltage Vh.
However, while the SCRs of FIGS. 3 and 4 are able to discharge a larger amount of current than the GGNMOS of FIGS. 1 and 2 when implemented within a similar area size, they commonly suffer from relatively high trigger voltage Vt values and relatively low holding voltage Vh values.